| 摘要 |
A method of fabricating a semiconductor device, which forms dielectric sidewalls reliably at each side of a first wiring structure to protect its conductive line in the etching process for forming a via hole in an interlayer dielectric layer to cover the first wiring structure. In this method, the first wiring structure is formed on a first dielectric layer. A second dielectric layer is formed on the first dielectric layer to cover the first wiring structure. A third dielectric layer serving as an interlayer dielectric layer is formed on the second dielectric layer. The third and second dielectric layers are polished using the CMP technique until the dielectric of the first wiring structure is exposed, thereby leaving part of the second dielectric layer that extends along each side of the first wiring structure and the surface of the first dielectric layer. The dielectric layer is etched using a mask to form a via hole. The hole is then filled with a conductive plug. A second wiring structure is formed on the remaining third dielectric layer in such a way that the second wiring structure is electrically connected to the first wiring structure through the plug. The second dielectric layer is less in polishing rate than the third dielectric layer in the CMP process. The second dielectric layer is less in etching rate than the dielectric of the first wiring structure in the etching process for the via hole.
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