| 摘要 |
A plurality of four bit modulation read only memory (ROM) codes are generated with a PLL feedback divider. The output of a single phase lock loop is modulated to spread the bandwidth of a synthesized clock signal. By spreading the bandwidth, the amplitude of the synthesized clock signal is decreased with respect to its fundamental and its harmonics. As a result of reducing the peak amplitudes, the radiated electromagnetic emission level is significantly lower. Input phase lock loop system data is received as to selected phase lock loop characteristics. A continuous FBD is selected, and a bandwidth and system stability calculation is performed. A state variable system is determined and a numerical model for programming by finite differences is developed. A best path is determined to produce output data and ROM code by a least squares error method.
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