| 摘要 |
PURPOSE: A method for fabricating a flash memory cell is provided to reduce parasitic capacitance and to improve an operation speed of the cell, by using a well fabricated by an electrical isolation and by using WSix to reduce well resistance of the well. CONSTITUTION: The first oxide layer(2), a pad polysilicon layer(3) and the first tungsten silicide layer(4) are sequentially formed on a semiconductor substrate(1). The first tungsten silicide layer, the pad polysilicon layer and the first oxide layer are patterned by an etch process using a cell well mask. The second oxide layer(5) is formed to fill a patterned portion, and the second oxide layer on the first tungsten silicide layer is removed by a blanket etch-back process. After the third oxide layer is formed, the third oxide layer is patterned by an etch process using a cell field mask. After a sub polysilicon layer(7) is formed, a chemical mechanical polishing(CMP) process is performed until the sub polysilicon layer on the third oxide layer is eliminated. A word line is formed, and a bit line is formed by an impurity ion implantation process.
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