| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory element which can reduce the number of masks used in formation of a lower electrode coupling and a bit line coupling and suppress the resistance increase of them, and its manufacturing method. SOLUTION: This technique can secure an incorrect lineup margin by forming a bit line coupling 216a, and a lower electrode coupling 228a which couple a bit line and a capacity lower electrode to the active regions of a semiconductor substrate, by making use of a self-aligned photoresist mask which is positioned on a source region 205 positioned on an interlayer dielectric 230 made all over the surface of the substrate 200, extends in the direction of extension of a gate G12, and exposes only one part of the interlayer dielectric into line form. A method of manufacturing a semiconductor memory element which forms each of the bit line coupling and the lower electrode coupling, making use of one time of a mask process. |
