PROCESS ELEMENT ARRAY LOGIC CIRCUIT AND FAST FOURIER TRANSFORM UNIT

摘要

PROBLEM TO BE SOLVED: To reduce the LSI area of a process element array logic circuit and power consumption for the circuit. SOLUTION: A process array element for the process element array logic circuit consists of a combination logic circuit 21 consisting of an exclusive nMOS network having two output terminals one of which is grounded and the other of which becomes high impedance corresponding to an input signal and a flip flop circuit 22 consisting of a CMOS inverter where a clock is impressed to a power source terminal by connecting two input/output terminals to the two output terminals of the circuit 21.