发明名称 Sample and hold phase detector having low spurious performance and method
摘要 A method for lowering the spurious output of a sample and hold phase detector includes the steps of charging a ramp node (502) to a first voltage level after a sample period (606) has occurred. After the ramp node (502) is charged to the first voltage level, the ramp node is charged to a second voltage level during period (610). By precharging the ramp node (502) during the hold period (614), it reduces any leakage current in the SH switch (514), which minimizes any voltage drift thereby improving the spurious performance of the SH phase detector (500).
申请公布号 US2002039020(A1) 申请公布日期 2002.04.04
申请号 US20010790377 申请日期 2001.02.22
申请人 BELLAOUAR ABDELLATIF;FRIDI AHMED R. 发明人 BELLAOUAR ABDELLATIF;FRIDI AHMED R.
分类号 H03D13/00;H03L7/091;(IPC1-7):G01R13/34 主分类号 H03D13/00
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