| 摘要 |
A pattern generator generates parallel pattern data and applies it to packet generating parts provided corresponding to row-address and column-address pins of a memory device under test. The pattern generator contains a packet select signal generating part that generates two packet select signals for generating respective cycle numbers in a sequence of cycles in an arbitrary packet period. In data setting parts provided corresponding to the row-address and column-address pins, respectively, bit positions of the data to be fed to the corresponding pins in the parallel pattern data are prestored in correspondence with the cycle numbers. In each cycle the bit positions corresponding to the cycle number are read out by the packet select signals corresponding to the row-address and column-address pins, and in the corresponding packet generating parts data bits corresponding to their bit positions in the parallel pattern data are selected and provided to the corresponding pins.
|
