发明名称 SYNCHRONIZATION CONTROL APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a synchronization control apparatus that can synchronously reproduce AC 3 coded data transferred via a USB without causing any hindrance to synchronization decision. SOLUTION: While received AC 3 coded data or 0 data are written in an FIFO buffer 23 synchronously with a bus clock, data not read yet are read from the FIFO buffer 23. When a difference between a quantity of data not read yet and synchronization point information is deviated from a permissible range, a synchronization decision section 204 controls a read rate to bring the difference within the permissible range. A synchronization point control section 205 detects top packet data of consecutive packet data arrived synchronously with the bus clock and controls the synchronization point information according to a period from the top packet data until succeeding to packet data.
申请公布号 JP2002084264(A) 申请公布日期 2002.03.22
申请号 JP20000273279 申请日期 2000.09.08
申请人 YAMAHA CORP 发明人 TOSHITANI TADASHI
分类号 G06F13/38;G11B20/14;H04J3/06;H04L7/00;H04L7/08 主分类号 G06F13/38
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