发明名称 Reducing lithography limitation by reverse-offset spacer process
摘要 A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.
申请公布号 US2002025638(A1) 申请公布日期 2002.02.28
申请号 US20010915659 申请日期 2001.07.26
申请人 UNITED MICROELECTRONICS CORP. 发明人 YEH WEN-KUAN;LIN TONY
分类号 H01L21/28;H01L21/336;(IPC1-7):H01L21/336;H01L21/823 主分类号 H01L21/28
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