| 摘要 |
PURPOSE:To enable a high speed action while reventing malfunction caused by noises by controlling an address buffer for forming and outputting an internal address signal for the prescribed period and by prohibiting a fetching of an external address signal or holding the previous signal. CONSTITUTION:For the period when a word selection timing signal becomes a high level and a word line is in the selected condition by means of a comparatively high action voltage, a timing signal phi and anti phi become low and high levels, respectively. Then FETs Q3 and Q4 of an address buffer for forming an internal address signal (ai), etc., from an external address signal Ai are turned on, and a fetching of the external address signal Ai is prohibited. Simultaneously, FETs Q9 and Q10 are turned on, and outputs of FETs Q5 and Q6 for forming an invertor are positively fed back, whereby the address signal fetched previously is held. As a result, a semiconductor memory device performs a high speed action while malfunction of the address buffer caused by comparatively large power source line noises, which occur due to an action of a data output buffer, is prevented. |
