| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital signal processor, with which the problem of limit cycle is solved in more simplified configuration. SOLUTION: In the digital signal processor provided with a digital filter part 3 equipped with a cyclic filter, when a zero data detecting part 2 detects zero data >= fixed time from input data A, a zero detection flag C is outputted, a coefficient value D of an attenuator part 4 is gradually decreased from 1.0 to 0 and when that coefficient value D becomes 0, the attenuator part 4 outputs a zero attenuate signal F. At such a time, a two-input NAND circuit 5 outputs a register clear signal G, registers 33 and 34 on the feedback side of the digital filter part 3 are cleared, output signals B thereof are turned to zero data and the coefficient value D of the attenuator part 4 is returned to 1. Thus, noises in no signal caused by the limit cycle can be avoided.
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