| 摘要 |
A data unit receives data packets and delivers them to packet switching circuitry. The data unit stores the received data packets in a memory. The memory has receive queues (RQ0 to RQ63) corresponding respectively to the different possible intended destinations of the receive packets in the packet switching circuitry, and when each data packet is received, an entry corresponding to the packet concerned is made in that one of the receive queues (RQ) which corresponds to the intended destination of the packets. A multicast handling section operates, when such a received data packet is a multicast packet having two or more intended destinations, to cause the packet registration means to make an entry corresponding to the multicast packet concerned in each receive queue corresponding to one of those destinations. An output section operates, for each receive queue, to read the entries in the queue concerned in the order in which they were made and, for each entry read, to read out the corresponding data packet form the memory and output it to the packet switching circuitry. Such a data unit is suitable for use in ATM switching apparatus in which the data packets each comprise one or more ATM cells, and can ensure cell sequence integrity for multicast and unicast cells having the same destination. Self-routing cross-connect switching devices for use in such ATM switching apparatus are also disclosed.
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