发明名称 Digital phase control using first and second delay lines
摘要 <p>A digital phase control method phase shifts a predetermined number of clock signals having the same frequency and having different phases at high precision and at high resolution as a whole with its phase interval maintained to keep a predetermined interval. The digital phase control method comprises the steps of preparing fourteen first multi-phase clock signals having a fixed phase, of preparing sixteen second multi-phase clock signals, of phase locking a specific clock signal of the fourteen first multi-phase clock signals with a particular clock signal of the sixteen second multi-phase clock signals, and of changing a combination of the specific and the particular clock signals to be phase-locked to phase shift the second multi-phase clock signals. In addition, in order to generate the second multi-phase clock signals, a delay line comprising ring-shaped chained delay buffers may be used.</p>
申请公布号 EP1178626(A2) 申请公布日期 2002.02.06
申请号 EP20010118624 申请日期 2001.08.02
申请人 NEC ELECTRONICS CORPORATION 发明人 NAKAMURA, SATOSHI
分类号 G06F1/06;G06F1/10;H03K5/04;H03L7/00;H03L7/07;H03L7/081;H03L7/083;H03L7/089;H03L7/099;H04L7/033;(IPC1-7):H04L7/033 主分类号 G06F1/06
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