| 摘要 |
PURPOSE: A high-speed DCT arithmetic circuit using distributed arithmetic is provided to enable high-speed DCT coefficient arithmetic to increase frame rate of a video compression system. CONSTITUTION: A ROM accumulator unit includes 2M ROMs(10,15,25,30) arranged in parallel at an input data side, an adder group, configured of a plurality of adders(45,50,55) that construct a tree structure, for adding up outputs of the 2M ROMs, and an accumulator register(70) for storing output data from the final adder of the adder group. The unit further has an adder(60) whose input port is connected to the output port of the final adder and whose output port is connected to the input port of the register, and a shifter(65) connected between the output port of the register and the input port of the adder. The ROM accumulator unit reads data items stored in the 2M ROMs simultaneously. |
