| 摘要 |
PROBLEM TO BE SOLVED: To prevent decrease in display quality and malfunction caused by power source noise by decreasing a peak current generated at a changing point of a display. SOLUTION: A display timing generation part 7 provided with a frequency divider circuit 21, a counter/decoder 22, and a combination circuit 23 is arranged. The display timing generation part 7 counts in excess of the minimum number of clocks necessary for displaying display clock signals, and generates a common signal CN for specifying one horizontal period based on the result obtained, and also generates a group of display timing signals TG1, a group of display timing signals TG2, a display data latch signal L1, and a display data latch signal L2 in a prescribed relation to one another. Circuit operation from latching a display data from internal circuit operation concerning a display output in display RAM 1 until the display data is outputted as a segment signal SM is completely divided into twos by generating these signal groups different in the signal timing, and thereby the peak current is distributed into the two.
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