MULTI-FUNCTION TIMER WITH SHARED HARDWARE

摘要

A multi-function timer (2) used to perform multiple input timing measurements and generate multiple timed output events on the I/O pins of the apparatus. The multi-function timer (2) comprises a plurality of slots (6) and a compute engine (3). Each of the slot(6) represents one of a plurality of timing processes. The compute engine (3) includes a micro-sequencer (10) and a processor (26). The micro-sequencer (10) identifies a current slot (6) and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots (6). The processor (26) performs the functions of the instructions associated with each current slot (6). Further, each slot (6) is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input. The multi-function timer (2) is advantageous in that it provides application design flexibility by eliminating the need for dedicated logic for input and output timing functions.