发明名称 |
Digital PLL (Phase-Locked Loop) frequency synthesizer |
摘要 |
The circuit compensates for phase error in the case of fractional-N-based PLL frequency synthesizers. All required actuating and reference signals are derived from the VCO frequency of the voltage-controlled oscillator by using an auxiliary phase-locked loop. The circuit is specifically applicable for HF-PLL frequency synthesizers using integrated circuit technology.
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申请公布号 |
US2001036240(A1) |
申请公布日期 |
2001.11.01 |
申请号 |
US20010799669 |
申请日期 |
2001.03.05 |
申请人 |
GOSSMANN TIMO;GOTZ EDMUND |
发明人 |
GOSSMANN TIMO;GOTZ EDMUND |
分类号 |
H03L7/07;H03L7/081;H03L7/183;H03L7/197;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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