| 摘要 |
The semiconductor device comprises an SOI substrate including a substrate (1), an embedded insulator layer (2) formed on the substrate, a semiconductor layer (3) formed on the insulator layer, a partial insulation layer (5b) formed in the vicinity of surface of the semiconductor layer and not in contact with the insulator layer, semiconductor elements such as MOS transistors (TR1, TR2) formed so to incorporate parts of semiconductor layer, and fictitious regions (DM1) not having function of elements, which are separated from semiconductor elements by the partial insulation layer and formed so to incorporate other parts of semiconductor layer. The SOI type device is presented in twelve enbodiments. The device comprises, as in the eleventh embodiment, a total insulation layer formed in contact with the embedded insulator layer and traversing the semiconductor layer, and the fictitious regions are separated from semiconductor elements by the total insulation layer. As impurity of predetermined conductivity type is injected in the semiconductor layer of the fictitious regions (3c). The device comprises, as in the second embodiment, fictitious interconnections on the surface of semiconductor layer of fictitious regions. The fictitious region comprises, as in the third, fourth, fifth, sixth, ninth, eleventh, and twelfth embodiments, a fictitious gate with an insulator layer formed on the surface of part of semiconductor layer, and a fictitious gate electrode formed on the insulator layer. The fictitious gate is formed on a part of semiconductor layer, and an impurity of predetermined conductivity type is injected in the portion of that part of semiconductor layer which is not covered by the fictitious gate. The fictitious gate, as in the eighth embodiment, is in the form of a cross, and the semiconductor layer of fictitious region constitutes a parallelogram having sides parallel to those of cross. The manufacturing method includes the following steps: (a) the preparation of SOI substrate including the specified layers; (b) the formation of partial insulation layer; (c) the formation of semiconductor elements such as MOS transistors; and (d) the formation of fictitious regions on other parts of semiconductor layer, simultaneously with the step (c). |
