PLL CIRCUIT AND IC FOR PLL, AND WIRELESS COMMUNICATION DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a PLL circuit that can reduce a phase noise. SOLUTION: The PLL circuit consisting of a 1st frequency divider means (6) that divides a frequency of a reference signal, a voltage controlled oscillator (113) whose oscillating frequency varies with a voltage level, a 2nd frequency divider means (7) that divides a frequency of an output signal of the voltage controlled oscillator and a phase comparator means that compares a phase of an output signal of the 1st frequency divider means with a phase of an output signal of the 2nd frequency divider means, is provided with a frequency pass band limit means (1) that limits a frequency pass band of the reference signal at an input path of the reference signal so as to reduce the phase noise.