发明名称 |
AUTOMATED REFERENCE CELL TRIMMING VERIFY |
摘要 |
A reference trimming verify circuit and method is provided for performing a program verify operation on a reference cell transistor in an array of Flash EEPROM memory cells. A reference current branch (14) is used to generate a reference current corresponding to a predetermined overdrive voltage of the reference cell to be programmed. A drain current branch (16) is coupled to the reference cell transistor to be programmed and generates a drain current at a fixed gate voltage applied to its control gate and at a predetermined drain voltage applied to its drain when the drain current is at the desired level. A comparator (18) is used to compare a sensed voltage corresponding to the drain current and a reference voltage corresponding to the reference current. The comparator generates an output signal which is at a low logic level when the sensed voltage is less than the reference voltage and which is at a high logic level when the sensed voltage is greater than the reference voltage. A program pulse is applied to the reference transistor each time the comparator generates the low logic level and terminates the program pulse when the comparator generates the high logic level.
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申请公布号 |
WO0169604(A2) |
申请公布日期 |
2001.09.20 |
申请号 |
WO2001US07983 |
申请日期 |
2001.03.12 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
PAN, FENG;BILL, COLIN, S. |
分类号 |
G01R31/28;G11C16/04;G11C16/34;H01L21/822;H01L27/04;(IPC1-7):G11C/ |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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