发明名称 DIGITAL PHASED ARRAY ARCHITECTURE AND ASSOCIATED METHOD
摘要 Digital phased array architecture and associated method are disclosed that eliminate the necessity of utilizing analog phase shifters in the receive and transmit signal paths. Desired delays are instead generated by adjusting the timing of sampling signals sent to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in the receive and transmit signal paths.
申请公布号 WO0167548(A2) 申请公布日期 2001.09.13
申请号 WO2001US06734 申请日期 2001.03.02
申请人 RAYTHEON COMPANY 发明人 FRAZIER, GARY, A.
分类号 H01Q3/30;H01Q3/26;H01Q3/38;(IPC1-7):H01Q3/26 主分类号 H01Q3/30
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