| 摘要 |
PROBLEM TO BE SOLVED: To provide functions of both a difference signal output circuit and a level converter circuit and to decrease the number of stages of logic elements or transistors that a signal passes through. SOLUTION: When an input signal has an L level, a 1st NMOS transistor N1 turns on with a 1st source potential VDL outputted from an inverter 41 and a 1st PMOS transistor P1 turns on to output a 2nd source potential VHD to a 1st output terminal 46 to output a reference potential VSS to a 2nd output terminal 47. When the input signal has an H level, an inverter 42 inverts the output potential of the inverter 41 to the 1st source potential VDL, a 3rd NMOS transistor N3 turns on to output the reference potential VSS to the 1st output terminal 36, and a 4th NMOS transistor N4 and a 2nd PMOS transistor P2 turn on to output the 1st source potential VDH to the 2nd output terminal 47.
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