| 发明名称 |
Method for shallow trench isolated, contacted well, vertical MOSFET DRAM |
| 摘要 |
A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
|
| 申请公布号 |
US6284593(B1) |
申请公布日期 |
2001.09.04 |
| 申请号 |
US20000705652 |
申请日期 |
2000.11.03 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MANDELMAN JACK A.;DIVAKARUNI RAMACHANDRA;RADENS CARL J. |
| 分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
