| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory in which reducing area and high speed operation can be realized. SOLUTION: Word lines WL of both arrays are selected by an index address 302 while sharing a data memory cell array 101 and a word line decoder/driver 111 of a tag memory cell array 201, and input/output of data is performed by a common data input/output circuit 123 by selecting a data input/output of the data memory cell array or a data input/output of the tag memory cell array.
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