发明名称 METHOD OF EXTRACTING CIRCUIT PARAMETERS, AND METHOD OF AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To enable highly precise calculation of finished wiring width and highly precise circuit simulation. SOLUTION: Correlation data 101 between the distance between model wiring and wiring existing around the model wiring in the same layer and the difference between the mask-layout width and the finished width of the model wiring are prepared, the wiring length and wiring width of analyzing wiring and the distance between the analyzing wiring and the wiring existing around the analyzing wiring in the same layer are extracted from the actual layout 100 (102), and wiring resistance value and wiring capacitance value with respect to the extracted layout-wiring width of the analyzing wiring and the extracted distance between the analyzing wiring and the wiring existing around the analyzing wiring are calculated by using finished wiring width obtained by referring to the correlation data (105).</p>
申请公布号 JP2001230323(A) 申请公布日期 2001.08.24
申请号 JP20000035267 申请日期 2000.02.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ISHIKURA SATOSHI
分类号 G03F1/36;G03F1/68;G03F1/70;G06F17/50;H01L21/027;H01L21/82;(IPC1-7):H01L21/82;G03F1/08 主分类号 G03F1/36
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