| 摘要 |
PURPOSE: To provide a semiconductor storage memory device which can reduce the pattern occupying areas of data registers by shortening random cycle time at writing time. CONSTITUTION: In the semiconductor storage memory device, the data registers 104-1 and 104-2 for latching written data are positioned closely to memory cells MC in a memory core section 100. Since data can be sent in advance to the upstream section of a data path for writing at the time of performing late writing operation, the random cycle time at writing time can be shortened by making the writing speed of data in a memory cell faster in the next write cycle. In addition, when a read command is inputted before the next write command is inputted and a consistency discriminating device detects address coincidence, the data latched in the data registers 104-1 and 104-2 are read out instead of the results of amplification by means of DQ read amplifiers 102-1 and 102-2, transferred to data lines RDe and RDo, and outputted to the outside.
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