Low power fractional pulse generation in frequency tracking multi-band fractional-N phase lock loop

摘要

Multi-band fractional-N PLL synthesizers with built-in spurious sideband compensation, which tracks the VCO output, tend to consume large amounts of power (as much as 10 times) due to the RF operation of the compensation circuitry. This patent introduces a dynamic power approach where the compensation circuitry is biased only during the fractional portion of the cycle. This technique provides the advantages of fractional-N synthesizers with spur suppression, such as higher speed and lower phase noise with ultra low power dissipation.