| 摘要 |
PURPOSE:To provide a variable delay quantity with high resolution. CONSTITUTION:One input of 1st and 2nd exclusive OR (EXOR) gates 17, 18 is connected to a delay input terminal 15, and both outputs are connected together through a capacitor 21. Moreover, the other input terminal of the 1st EXOR gate 17 connects to ground, the other input terminal of the 2nd EXOR gate 18 is connected to a selection signal input terminal 19 and an output of the 1st EXOR gate 17 is connected to a delay output terminal 16 through a logic buffer 22. When a level of a selection signal is '0', potentials across the capacitor 21 are always at an equi-potential and no current flows to the capacitor 21, and when the level of the selection signal is '1', a current flows to the capacitor 21 and the current is delayed by a prescribed quantity with respect to an output of the output terminal 16 when the level of the selection signal is '0'. |
