发明名称 |
Testing error correcting code feature in computers that do not have direct hardware features for causing single bit and multi-bit errors |
摘要 |
Built-in tests included in reset functions of single board computers can be rapidly performed to confirm adequate functionality without additional hardware support by disabling an error correcting code function in a memory controller, writing a pattern of predictable parity to a location in memory and reading and correcting the pattern with the error correcting code function of the memory controller re-enabled. Thus, resets caused by, for example, momentary soft errors or power interruptions can be executed within rigid time constraints and thus negligibly short interruptions of processor function. |
申请公布号 |
US6237116(B1) |
申请公布日期 |
2001.05.22 |
申请号 |
US19980192310 |
申请日期 |
1998.11.16 |
申请人 |
LOCKHEED MARTIN CORPORATION |
发明人 |
FAZEL MAGID;PORTER LINDA A. |
分类号 |
G06F11/10;G06F11/14;G06F11/267;(IPC1-7):G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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