发明名称 |
Apparatus and method for detecting two data bits per clock edge |
摘要 |
A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of said first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.
|
申请公布号 |
US6232796(B1) |
申请公布日期 |
2001.05.15 |
申请号 |
US19990358054 |
申请日期 |
1999.07.21 |
申请人 |
RAMBUS INCORPORATED |
发明人 |
BATRA PRADEEP;SIDIROPOULOS STEFANOS |
分类号 |
G11C7/10;H03K5/08;H03K5/135;(IPC1-7):H03K19/00;H03K3/289 |
主分类号 |
G11C7/10 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|