| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory having a simple data bus structure whose circuit scale can be reduced and whose output data width can be switched. SOLUTION: A pre-decoder band + selector band 54#1 outputs selection signals SEL0-SEL7 and WORDA-WORDC to a pre-amplifier + write driver band 62#1 according to an output data width switching mode signal. The pre- amplifier + write driver band 62#1 can switch a connection relation between global IO lines GIO<0>-GIO<7> and a data bus 56#1 according to the selection. The read data are outputted to a pad 13 without any interposed selector circuit or the like in the middle on a data bus. Thus, it is not necessary to adjust any critical delay time due to mode switching or address change, and it is possible to realize a simple constitution. |
