| 摘要 |
A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with an FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio . In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.
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