发明名称 Open loop supply independent digital/logic delay circuit and method
摘要 A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.
申请公布号 AU4843900(A) 申请公布日期 2001.04.23
申请号 AU20000048439 申请日期 2000.05.11
申请人 CIRRUS LOGIC, INC. 发明人 VISHNU S. SRINIVASAN;JOHN PACOUREK;JOHN JAMES PAULOS
分类号 H03F1/30;H03K5/00;H03K5/13;H03M3/02 主分类号 H03F1/30
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