| 摘要 |
PROBLEM TO BE SOLVED: To provide a parallel processor improving the use efficiency of an expansion instruction in processing a single operation. SOLUTION: An operation mode register 1151 stores an operation mode showing whether or not to parallelly operate a coprocessor, an instruction register 113 transfers an integral processing unit instruction to a decoding part 114 in a single operation mode, an executing part 116 executes the integral processing unit instruction, and a no-operation instruction is also generated and outputted to a data processing unit 12 without embedding the no-operation instruction in an instruction regulating the operation of the unit 12 to make the unit 12 a processing stopped state. Meanwhile, in a parallel processing operation mode, the data processing unit instruction is outputted to the unit 12 to be subjected to data processing.
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