| 摘要 |
<p>The invention proposes a phase detector (90) for a phase-locked loop. In this context, it relates to an improvement in the phase detector (90) which can be used in a digital PLL circuit. The invention consists in a sampled and digitized data signal being supplied to the phase detector (90) as an input signal. This data signal is delayed by a sampling clock signal in a delay stage (52). The delayed data signal and the undelayed data signal are then supplied to a subtraction stage (53). The difference between the two input values is formed in this subtraction stage. The differential value determined is then analysed in a processing stage (54) and one of a plurality of possible values is assigned to it. This is done on the basis of the value range in which the differential value is situated. The assigned value is then passed on as an output value to a filter/control stage (60), at whose output a phase error can then be tapped off. The solution described can be integrated very easily on a chip and affords a very advantageous response for the PLL control.</p> |
