发明名称 Frequency multiplier capable of taking out efficiently and stably harmonics higher than fourth order
摘要 One end of a first transmission line is connected to the collector of an HBT with the base connected to an output terminal of an input-side matching circuit and with the emitter grounded, and one end of an end-open stub for blocking the passage of the doubled wave is connected to the other end of the first transmission line. One end of a second transmission line is connected to the other end of the first transmission line, and one end of an end-open stub for blocking the passage of the fundamental wave is connected to the other end of the second transmission line. An input terminal of an output-side matching circuit is connected to the other end of the second transmission line. The fundamental wave is reflected toward the HBT at the connecting point of the end-open stub for blocking the passage of the fundamental wave, while the doubled wave is reflected toward the HBT at the connecting point of the end-open stub for blocking the passage of the doubled wave, by which only harmonics of quadrupled wave or higher-ordered waves are outputted via the output-side matching circuit. Thus, the frequency multiplier is capable of taking out fourth- or higher-ordered harmonics efficiently with a simple constitution using one high frequency transistor, and can be reduced in size and stabilized in operation.
申请公布号 US6198365(B1) 申请公布日期 2001.03.06
申请号 US19990440762 申请日期 1999.11.16
申请人 SHARP KABUSHIKI KAISHA 发明人 YAMADA ATSUSHI
分类号 H01P1/203;H03B19/14;H04B1/04;(IPC1-7):H03H11/04 主分类号 H01P1/203
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