主权项 |
1. A processor comprising:
a plurality of packed data registers; a decoder to decode an instruction, the instruction to indicate a first source packed data that is to be stored in the plurality of packed data registers and that is to have a first plurality of packed data elements, to indicate a second source packed data that is to be stored in the plurality of packed data registers and that is to have a second plurality of packed data elements, each of the data elements of the first source packed data to correspond to a different one of the data elements of the second source packed data in a corresponding position; and an execution unit coupled with the decoder and the plurality of packed data registers, the execution unit in response to the instruction, to store a packed data result in a destination packed data register of the plurality of packed data registers, the packed data result to include a plurality of result data elements, each of the result data elements to correspond to a different one of the data elements of the first source packed data in a corresponding position, and to correspond to a different one of the data elements of the second source packed data in a corresponding position, wherein: result data elements that correspond to positive data elements of the second source packed data are to store values of the corresponding data elements of the first source packed data; and result data elements that correspond to negative data elements of the second source packed data are to store negated values of the corresponding data elements of the first source packed data. |