| 摘要 |
PROBLEM TO BE SOLVED: To freely select the relation between a clock frequency and an output frequency. SOLUTION: A frequency synthesizer is provided with an extended accumulator 1 for inputting setting data K which is a natural number, setting data M of a natural number greater than the setting data K and the clock signal of a clock term T, cumulatively adding the setting data K each time the clock signal is inputted, outputting an overflow signal OF when the cumulatively added result reaches the setting data M, performing cumulative addition again with a value subtracting the setting data M from the cumulatively added result as an initial value, and outputting the cumulative added result, namely, an output signalθ, a data converting circuit 2 for inputting the setting data M and the output signalθand calculating out a control signal M-θ, a delay generator 3 for delaying the pulse of the overflow signal OF by a delay time (M-θ)/K} T+τ, when an arbitrary constant time is defined asτand an output circuit 4 for inputting the output pulse of the delay generator 3 and outputting it, while the pulse width is fixed.
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