发明名称 WIRING BOARD, MULTILAYER WIRING BOARD, CIRCUIT COMPONENT PACKAGE, AND MANUFACTURING METHOD OF WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To easily manufacture high-density wiring at low costs by filling a conductive material into the second via hole of an insulation layer whose sectional area is smaller than that of a first via hole of a base layer and which is partially buried, and the first via hole. SOLUTION: On both the surfaces of a base layer 101 with a first via hole 103, an insulation layer 104 with a second via hole 105 of which sectional area is smaller than the first via hole is provided. Then, on the via hole 105, a wiring layer is formed by a via pad 106 and wiring 107. Upper and lower wiring layers 107 and 107 are electrically bonded by the first and second via holes 103 and 105 for forming a double-sided wiring board as a whole. A conductive material is filled into a via hole 102 consisting of the first and second via holes 103 and 105. Also, wiring 107 is formed on the insulation layer 104, thus reducing the size of the second via hole 105 and a via pad 106, and hence achieving high density regardless of the sectional area of the first via hole 103.</p>
申请公布号 JP2001028483(A) 申请公布日期 2001.01.30
申请号 JP20000175838 申请日期 2000.06.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TSUKAMOTO KATSUHIDE
分类号 H05K3/20;H01L21/60;H01L23/12;H01L23/31;H01L23/498;H05K1/11;H05K1/18;H05K3/00;H05K3/28;H05K3/40;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/20
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