| 摘要 |
<p>The present invention provides a parallel bus system for expanding peripheral devices, which comprises a central processing unit (21), at least one peripheral device (22, 23, 24), and a parallel bus (20) for connecting the central processing unit (21) and the at least one peripheral device (22, 23, 24). One line of the parallel bus is used as the peripheral device selecting line, and another line of the parallel bus is used as the system clock line. Other lines of the parallel bus are lines to form one byte of the system. The messages flowing on the other lines include instruction bytes, address bytes, and data bytes. In general, instruction bytes are first be put on the other lines, followed by address bytes, and then data bytes. <IMAGE></p> |
