| 摘要 |
PURPOSE: A semiconductor memory device is provided to selectively sense and amplify a bit line or a vice-bit line only, reduce a sensing current being consumed when sensing and amplifying, and reduce load of a sense amplifier, thereby improving operation speed CONSTITUTION: The device includes a large number of memory cell arrays, a sense amplifier(220), a delaying portion(270), a control signal generating portion(260), and first and second separating portions(230,240). The memory cell arrays is a matrix form in which word lines and bit lines and vice-bit lines are each other crossed, and is that the unit memory cell is arrayed with a folded bit line architecture. The sense amplifier senses and amplifies a voltage difference of the bit line and the vice-bit line. The delaying portion delays the address signal for a predetermined time. The control signal generating portion outputs fourth through seventh control signals connecting the bit line or the vice-bit line to the sense amplifier selectively. The first separating portion separates the bit line and the vice-bit line of the first memory cell array from a line for sensing and amplifying and a vice-line for sensing and amplifying of the sense amplifier. The second separating portion separates the bit line and the vice-bit line of the second memory cell array from the line and the vice-line for sensing and amplifying.
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