发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit that decreases lockup time and obtains C/N ratio which is affected less by an external noise. SOLUTION: This phase-locked loop PLL circuit is provided with a control circuit 3 to allow the PLL circuit to discriminate whether it is in a locked state or an out of lock state on the basis of an output voltage Vf of a loop filter 2 and to provide the output of an output control signal S1 and with a variable gain amplifier, whose gain is changed by the output control signal S1 to generate a control voltage Vc and to give it to a VCO5. Thus, when the oscillated frequency of the VCO5 indicates out of lock state, the lockup time can be decreased and when the oscillated frequency fv is close to a desired frequency, a high C/N ratio can be obtained.
申请公布号 JP2000341117(A) 申请公布日期 2000.12.08
申请号 JP19990146718 申请日期 1999.05.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 SHIROTSU TETSUYA
分类号 H03L7/107 主分类号 H03L7/107
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