METHOD AND APPARATUS FOR PLL WITH IMPROVED JITTER PERFORMANCE
摘要
An apparatus is described having a current source (520) and a pair of transistors (510a, 510b) coupled to the current source. A pair of variable loads (Ra, Rb) are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads is coupled to a high gain input (501a) and a low gain input (501b).
申请公布号
WO0070766(A1)
申请公布日期
2000.11.23
申请号
WO2000US13720
申请日期
2000.05.19
申请人
PARTHUS TECHNOLOGIES PLC;SILICON SYSTEMS (US), INC.;SMYTH, MARK, M.;FOLEY, DAVID, J.;HORAN, JOHN;RYAN, JOHN, G.
发明人
SMYTH, MARK, M.;FOLEY, DAVID, J.;HORAN, JOHN;RYAN, JOHN, G.
