| 摘要 |
PURPOSE: An adaptive scan chain for debugging and testing an integrated circuit is provided to reduce a test time by debugging an integrated circuit chip in JTAG(Joint Test Action Group) condition using a multiple scan chain. CONSTITUTION: A scan chain circuit is provided to test a plurality of function blocks. In a first test mode, the scan chain circuit has a plurality of scan chains, wherein each scan chain is provided for scanning data inside and/or outside one or more corresponding function block. In the test operation, one of the scan chains is scanned to test. In a second test mode, the scan chain circuit has a plurality of scan chains are scanned in parallel in a test operation. Each scan chain scans inside and/or outside corresponding one or more function block.
|
