| 摘要 |
PURPOSE: A wire-arrayed chip size package is provided to have the size of the wire-arrayed chip size package have almost the same size of a semiconductor chip and to easily have the package have multi pins, by using a more finite wire than a conventional solder ball, and by performing a direct wire bonding between a chip pad and a metal pattern portion. CONSTITUTION: A wire-arrayed chip size package comprises a semiconductor chip(102), an insulating tape(108), a metal pattern portion(110), a solder mask(112), a metal pattern portion-electrolytic plating(111), a wire(118,120), a wire-electrolytic plating, and a molding resin. The semiconductor chip has a plurality of chip pads. The insulating layer tape has a plurality of holes, having the semiconductor chip adhered to a bottom surface. The metal pattern portion is formed on the insulating layer tape. The solder mask is formed to cover a part of the insulating layer tape and metal pattern portion. The metal pattern portion-electrolytic plating is formed on the surface of the metal pattern portion not covered with the solder mask. The wire electrically connects the chip pad with the metal pattern portion-electrolytic plating. The wire-electrolytic plating is formed on the surface of the wire. The molding resin(116) surrounds the side and bottom surfaces of the semiconductor chip. |
