| 摘要 |
A memory device has address, data, and control buses, and a memory-cell array including a number of memory cells arranged in rows and columns, each memory cell operable to store a bit of data. A row address decoder circuit is adapted to receive a row address applied on the address bus and operates to decode the row address and activate a row of memory cells corresponding to the decoded row address. A column address decoder circuit is adapted to receive a column address applied on the address bus and operates to decode the column address and access a plurality of memory cells in the activated row. The data stored in the plurality of memory cells in the activated row is defined as a block of data. A precharge circuit is coupled to the memory-cell array and operates, when activated, to precharge and equilibrate the memory-cell array. A block read latch circuit operates to latch a first block of data accessed in the memory-cell array corresponding to first decoded row and column addresses, and to sequentially transfer subblocks of the first block of data onto the data bus. The memory device operates such that after the first block of data is latched in the block read latch, the precharge circuit first precharges and equilibrates the memory-cell array, and the row and column decoder circuits then decode second row and column addresses such that the column address decoder circuit accesses a second block of data corresponding to the second row and column addresses before the block read latch circuit has completed sequentially transferring all the subblocks of the first block of data onto the data bus. The memory device may further include a block write latch circuit adapted to sequentially receive on the data bus subblocks of data contained in a first block of data to be written to the memory-cell array.
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