摘要 |
PROBLEM TO BE SOLVED: To provide a recording code capable of reducing a maximum inverting interval and decreasing a DC component by performing non-return-to-zero(NRZ) recording by converting 16 bits to 24 bits. SOLUTION: Four kinds of tables P, Q, R and S incorporated with a ROM 2 for 16-24 modulation have the number of continuous bits in the same code of 2 to 8 bits and the same characteristics as codes 1 and 7. In order to stably lock a phase locked loop(PLL), the total number of data having the number of continuous bits for 2 bits is made to less than (i) bits among 24 bits. A comparative selector circuit selects the optimum table out of four kinds of tables P, Q, R and S.
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