| 摘要 |
PROBLEM TO BE SOLVED: To provide a sum and comparator circuit minimizing propagation delay, and minimizing the amounts of a die area required for executing the sum and comparator circuit. SOLUTION: In this sum and comparator circuit equipped with a propagation/ generation block 12 followed by a carry look-ahead tree structural body 14, the propagation/generation block 12 receives a first operand A equivalent to an addend, a second operand B equivalent to an augend, and a third operand J equivalent to the complement of 2 of a constant K, and includes a logic constituted so that a first sum can be obtained by adding the operand A to the operand B and a logic constituted so that plural propagation signals and generation signals to be outputted from the propagation/generation block 12 to the carry look-ahead tree structural body 14 can be obtained by adding the first sum to the operand J, and the carry look-ahead tree structural body 12 includes a logic constituted so that an output GOUT can be prepared by calculating the propagation and generation signals. The output GOUT can be obtained by analyzing so that whether or not a formula A+B>=K is true can be decided. |
