发明名称 POLY-GATE ELECTRODE FORMING METHOD
摘要 PROBLEM TO BE SOLVED: To make a gate electrode width narrow for attempting minimization by forming the gate electrode made of poly-silicon by a resist pattern having an exposure limit size width by using an i beam light source, by oxidizing up to a predetermined depth from the surface and by eliminating an oxidized region. SOLUTION: A silicon oxide film 2 and a poly-silicon film 3 are formed by laminating on a semiconductor substrate 1. A resist mask 4 is formed on the poly-silicon film 3 and this is imagined as a minimum width by an i beam exposure device, for example a pattern of 0.365μm. Next the poly-silicon film 3 is eliminated by etching and a required film thickness is made to remain. Next the semiconductor 1 is entered in oxygen atmosphere to be heated and the poly-silicon film 3 is oxidized from the surface side. In the case oxidation is made from the poly-silicon film 3 remained while the etching to reach the silicon oxide film 2 and an oxide region 7 having a required film thickness is formed on the whole surface. After that all the oxidized region 7 is eliminated by etching.
申请公布号 JP2000236091(A) 申请公布日期 2000.08.29
申请号 JP19990037042 申请日期 1999.02.16
申请人 NKK CORP 发明人 NISHIGAYA TAKEHIKO
分类号 H01L29/78;H01L21/28;(IPC1-7):H01L29/78 主分类号 H01L29/78
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