| 摘要 |
PURPOSE: A predecoder circuit for minimizing power consumption is provided to reduce power consumption by selectively resetting a memory cell word line or a bit line by means of a second predecoder. CONSTITUTION: A plurality of banks include banks (12, 14, 16, 18). A clock buffer circuit (15) receives an external clock signal and generates a pulse clock signal to be operated as a reference operation signal of a synchronous semiconductor memory device. An operation control signal generator (20) combines control signals inputted from an external source after being synchronized with a pulse clock signal, and generates a low active signal and a low precharge signal. An address buffer circuit (30) buffers bank signals inputted from an external source after being synchronized with the pulse clock signal and generates preliminary bank signals. A bank buffer circuit (40) generates preliminary decoding address. A low predecoder enable signal generator (60) generates a low predecoder enable signal to select a particular bank. A low predecoder reset signal generator (70) generates a low precharge reset signal to precharge a sub-block of a selected bank with a reset. A low pre-decoder (80) selects or precharges a memory cell word line of a selected bank.
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